1. Field of the invention
The present invention relates to a highly integrated semiconductor connecting device and a method for making the same, and more particularly to improvements in integration degree of a semiconductor device along with a semiconductor connecting device and a method for making the same.
2. Description of the Prior Art
For convenience's sake, description which will be given next for a conventional connecting device and method is confined within a connecting device comprising a bit line to be connected with a drain region in the structure of a dynamic random access memory (DRAM) cell, in which a bit line connected with a drain region is formed in advance of a capacitor connected with a source region.
Generally, for the sake of forming a gate region and source/drain electrodes in one active region and connecting a bit line with the drain region in advance of forming a charge storage electrode contact in the source region, the bit line is positioned above a device separation insulating film which is between the source regions in such a way not to be placed above the source region or to minimally overlap with the source electrode. However, in case that a bit line contact and a charge storage electrode contact, when forming a bit line to be connected with the drain region, are linearly positioned on the same line with the bit line, since the bit line is sufficiently connected with the bit line contact formed in the drain region and the neighboring bit lines are to be spaced apart, the bit line neighboring the bit line connected with the drain region is positioned above the neighboring source region, at last.
A conventional DRAM cell is to be described with reference to a few figures for the better understanding of the prior art.
Referring initially to FIG. 1, there is a schematic plan view showing only important mask layers for fabricating a DRAM cell, in which a bit line connected with a drain region is formed in advance of a capacitor connected with a source region according to a conventional method. While reference numeral 1 designates an active region mask in the figure, reference numerals 2, 3 and 4 designate a bit line contact mask, a bit line mask and a charge storage electrode contact mask, respectively. As illustrated in this figure, the drain region which is formed at a lower part than the source in an active region 1a is connected with the bit line 3, so that the bit line 3 is scarcely positioned above the source region in which the charge storage electrode contact 4. However, as the drain region is extended below the source region in which the charge storage electrode 4 is formed, two active regions 1b and 1c positioned below the drain region have to be at some distance each other in order that the drain region Keep apart from the active regions positioned below, causing the area of cell to increase.
For more detailed description, FIGS. 2A to 2C are referred to, which are schematic cross-sectional views illustrating the steps for forming the bit line in a DRAM cell according to a conventional method, respectively, taken generally through section line A--A ' of FIG. 1.
First, as shown in FIG. 2A, over a predetermined portion of a semiconductor substrate 5, an active region and a device separation insulating film 6 are formed, followed by the formation of a gate region (not shown), a source region (not shown) and a drain region 7 over the active region. An interlayer insulating film 8 is formed entirely on the resulting structure. At this time, the active region where the drain region is formed is formed in such a way to be extended below another active region where the source region is formed (refer to FIG. 1).
Subsequently, a bit line contact hole is formed on a predetermined portion of the drain region 7 and then, a conductive material for bit line 14 is entirely deposited over the resulting structure, as shown in FIG. 2B. At this time, the bit line contact is to be positioned below the charge storage electrode contact formed in the source region at later process, as shown in FIG. 1.
Finally, using the bit line mask 3, the conductive material for bit line 14 is etched so partly as to form a bit line 16, as shown in FIG. 2C. The bit line is connected with the drain region 7 which is formed below the active region where the source region is formed, so that the bit line 16 is scarcely positioned above the source where the charge storage electrode is formed.
However, By the above conventional method, the drain region is formed in such a way to keep apart from the two neighboring active regions linearly positioned below the drain region, which are forced to be at some distance each other, causing the area of cell to increase.